semiconductors
INCOMPLETECoverage incomplete — the monitor is missing feeds for semiconductors, so no score is shown. Incomplete coverage is not zero risk.
Guided scenario
What if a major earthquake hits Taiwan?
Taiwan holds nearly 80% of EUV-generation foundry capacity and about 46% of total global foundry capacity — TSMC alone is 72% of foundry revenue. Three measured quakes (1999, 2016, 2024) show the range from overnight recovery to a 5× DRAM spike. Model the shock yourself.
1The setup
Taiwan holds nearly 80% of EUV-generation foundry capacity (7nm and beyond) and about 46% of total global foundry capacity — the world's chip supply has a single geographic keystone. Three measured shocks calibrate the range: the 1999 Chi-Chi quake (M7.6) halted all 28 Taiwan fabs, TSMC scrapped 28,000 wafers at a cost of $88.2M, and spot DRAM traded roughly 5× early-July prices; the 2016 Meinong quake (M6.4) delayed ~100,000 12-inch wafers by 10–50 days with no guidance cut; the 2024 Hualien quake (M7.4) saw >70% of tools recover within 10 hours and guidance held. The pattern: damage, not shaking, sets the outcome — and an M8.0+ shock would be beyond the measured analogs. Use the magnitude dial to move between the resilient case and the no-precedent case.
2Right now
Monitor data as of Sep 24, 2026. Scores are observed readings, not forecasts.
How the shock travels
Wafers scrapped
Tools stop mid-process and in-process wafers are often unsalvageable: TSMC scrapped 28,000 wafers in 1999 at a cost of $88.2M, leaving a multi-week output hole behind a multi-month pipeline.
Evidence: EDN on the 1999 Chi-Chi quake — TSMC scrapped 28,000 wafers, $88.2M in damaged goods and lost sales
Lithography recalibration
Fab buildings largely survive a quake, but ultra-sensitive lithography optics and exposure tools are thrown out of alignment — recalibration takes days before tools can restart.
Evidence: EE Times on the 1999 quake — days of lithography recalibration before fab restart
Spot price spike
1999's shortage repriced within days: spot DRAM rose ~37% in a week and traded roughly 5× early-July prices; Beijing retail memory-module prices jumped 20% the following week.
Evidence: EE Times/EDN spot-market reporting, Sep 1999 — 64-Mbit modules $15.50 to $21.25 in days, ~5× from the pre-shock baseline
Power outage compounds the stoppage
The 1999 quake triggered a Taiwan-wide power outage that kept fabs down beyond the shaking itself — the grid, not the building, was the binding constraint.
Evidence: EDN on the 1999 quake — island-wide outage extended fab downtime
OEM panic-buying
Analysts warned in 1999 that order acceleration by device makers could extend shortages into the following year — the behavioral amplifier on top of the physical one.
Evidence: 1999 analyst warnings — a plausible mechanism with no measured figure
Caveat: UNVERIFIED as a measured figure — no verified data exists on the scale of 1999 order acceleration
3The exposure
Coverage incomplete — the monitor does not track exporter shares for semiconductors. The exposure for this scenario is sized from the declared capacity snapshot in the “Adjust the assumptions” section below instead.
How the shock travels
Follow the shock downstream — from the semiconductors market, through processors, to the shelf. These are the usual stages, not this scenario's outcome: exposure at each step, never a prediction.
Day 0: foundry tools stop, in-process wafers scrapped
timing not establishedLag basis: Day 0 is the shock itself — tools stop mid-process and in-process wafers are often unsalvageable. The taiwan-quake guide's 1999 Chi-Chi analog: all 28 of TSMC's fabs halted and 28,000 wafers were scrapped ($88.2M).
logic wafersadvanced-node wafersTaiwan Semiconductor Manufacturing
TSMDedicated semiconductor foundry; its 2025 20-F states: “We manufacture a variety of semiconductors based on designs provided by our customers.”
Source: TSMC 2025 20-F (SEC)
Fabless designers — no wafers, no shipments
typically weeks to months →Lag basis: 1999 Chi-Chi analog (scenario's own transmission evidence): the halt left a multi-week output hole behind a multi-month pipeline; spot DRAM repriced within days.
GPUsCPUsnetworking chipsNVIDIA
NVDAFabless designer; its FY2026 10-K states it “depend[s] on foundries to manufacture our semiconductor wafers,” naming TSMC and Samsung.
Source: NVIDIA FY2026 10-K (SEC)
Advanced Micro Devices
AMDFabless designer; its 2025 10-K states it uses third-party foundries “to fabricate the silicon wafers for all of our products,” relying on TSMC for 7nm-and-smaller nodes.
Source: AMD 2025 10-K (SEC)
Broadcom
AVGOFabless designer; its 2025 10-K states the majority of front-end wafer manufacturing is outsourced to external foundries, including TSMC.
Source: Broadcom 2025 10-K (SEC)
Chip test and equipment — demand shock
timing not establishedLag basis: lag not established in sources reviewed
semiconductor test equipmenttest servicesTeradyne
TERSemiconductor test-equipment maker; its 2025 10-K states that disruption of the global semiconductor industry would adversely impact its business and revenues.
Source: Teradyne 2025 10-K (SEC)
Illustrative scenario. Not a prediction. Not financial advice. Company entries describe factual exposure to the commodity — not a view on any stock.
Trade map
Who ships it, who can’t do without it
2024 vintage · annual data, 1–2y lagSourced trade structure — the scenario’s shock geography at country resolution. Exposure, not a forecast.
Semiconductors · Taiwan
Top exporters
Taiwandominant
24.19% of world exports
China
18.35% of world exports
South Korea
15.14% of world exports
Malaysia
8.34% of world exports
Singapore
7.98% of world exports
Note: HS22 8542 electronic integrated circuits (BACI 2024). Hong Kong and Singapore are re-export/entrepot hubs — gross flows overstate origin, so BACI-reconciled OEC data used, not raw Comtrade. Taiwan (Chinese Taipei) reports no Comtrade data; all TW figures are OEC/BACI-derived.
Exposed importers
Shocked exporters: Taiwan
49.34% of Singapore’s semiconductors imports come from Taiwan
30.93% of China’s semiconductors imports come from Taiwan
20.21% of Hong Kong’s semiconductors imports come from Taiwan
Taiwan Strait / East Asia chip lane
via Taiwan Strait (no single maritime chokepoint for chip trade)
No single corridor — share not applicable — Disclaimed by the corridor's own note: no single maritime chokepoint for chip trade. No route share applies -- this is not missing research.
How we map this
Exporter and importer shares are 2024 vintage · annual data, 1–2y lag from UN Comtrade and OEC (BACI/CEPII); an importer counts as exposed when ≥20% of its semiconductors imports come from a shocked exporter. The shock geography is the scenario’s own focus selection. Annual data with a 1–2 year reporting lag — the structure moves slowly, the prices don’t.
In a famous portfolio
ARK Innovation ETF
2026-09-1742 holdings
daily holdings disclosure · published 2026-09-17
5 of 42
disclosed holdings sit in semiconductors’s curated shock path.
Mapped to our current coverage — not total portfolio risk.
ADVANCED MICRO DEVICES
#12 holdingAMDFabless designer; its 2025 10-K states it uses third-party foundries “to fabricate the silicon wafers for all of our products,” relying on TSMC for 7nm-and-smaller nodes.
Source: AMD 2025 10-K (SEC)
NVIDIA CORP
#14 holdingNVDAFabless designer; its FY2026 10-K states it “depend[s] on foundries to manufacture our semiconductor wafers,” naming TSMC and Samsung.
Source: NVIDIA FY2026 10-K (SEC)
BROADCOM INC
#22 holdingAVGOFabless designer; its 2025 10-K states the majority of front-end wafer manufacturing is outsourced to external foundries, including TSMC.
Source: Broadcom 2025 10-K (SEC)
TAIWAN SEMICONDUCTOR-SP ADR
#33 holdingTSMDedicated semiconductor foundry; its 2025 20-F states: “We manufacture a variety of semiconductors based on designs provided by our customers.”
Source: TSMC 2025 20-F (SEC)
TERADYNE INC
#35 holdingTERSemiconductor test-equipment maker; its 2025 10-K states that disruption of the global semiconductor industry would adversely impact its business and revenues.
Source: Teradyne 2025 10-K (SEC)
How we map this
Holdings: ARK Innovation ETF 2026-09-17 daily holdings disclosure, published 2026-09-17 — ARK Invest daily holdings (CSV). ARK publishes its full holdings daily. Figures are from the file dated September 17, 2026. Four disclosed positions without a listed ticker are excluded from the mapping. We map only to companies with curated, sourced exposures — a holding absent here is not a claim of no exposure.
4Adjust the assumptions
Earthquake magnitudeM7.5–7.9
Historical check: No semiconductors episode on record — no historical range to compare this setting against.
What share of the exposed capacity is disrupted.
Resolution: Moment magnitude reported by the USGS
Share of global foundry revenue in the hazard zone
0%50%100% global foundry revenue
Global foundry revenue (TSMC) — 72.0% of global foundry revenue
Exposed under your assumptions: 43.2% (72.0% × 60% severity)
The hatched area is modeled from your assumptions, not a measured outcome.
Source: Counterpoint Q3 2025 (72.0%) / TrendForce Q2 2026 (72.5%)
Exposed ≠ lost — affected trade can reroute, draw stocks, or substitute. This sizes the exposure, not the damage.
30d
Historical check: No semiconductors episode on record — no historical range to compare this setting against.
Resolution: Days until TSMC wafer shipments return to schedule (TSMC investor-relations disclosures)
60d
Your assumption — not a measured buffer.
Resolution: Assumed days of stockpile cover — an assumption, not a measured buffer
Disruption timeline
090180270365 days
Disruption: 30 days
Assumed cover: 60 days — your assumptionYour assumption
Covered by stockpiles— the assumed cover outlasts the disruption
What this would have meant
At these settings, about 43.2% of the world's semiconductors exports would be exposed to the disruption, and the 60-day assumed stockpile cover outlasts the 30-day disruption.
No close historical match in our records — this scenario is outside our recorded experience.
What this assumes
- Exposure: Target share 72.0% × severity 60% = 43.2% exposed.
- Uncovered days: max(0, 30 − 60) = 0.
- Exposed ≠ lost: affected trade can reroute, draw down stocks, or find substitutes — this number sizes the exposure, not the damage.
- Exporter share ≠ spare capacity: rivals may not be able to surge supply to fill the gap.
- Stockpile cover of 60 days is your assumption, not a measured buffer.
- Results are physical-exposure arithmetic from your stated assumptions — not a price forecast.
Analog check
No close historical match in our records — this scenario is outside our recorded experience.
Want the full controls? Reopen semiconductors on its commodity page.
5What happened before
For perspective, not prediction
What to watch
- USGS magnitude and location — the 1999 Chi-Chi quake was M7.6, Hualien 2024 M7.4
- TSMC's post-quake statement: which tools were damaged vs. merely idled — in 2024 all EUV tools survived
- TSMC investor-relations disclosures of wafer-delivery delays — the grading line is ≥10-day delays at any leading-edge fab or a guidance cut
- Spot DRAM pricing — in 1999 the repricing landed within days, not weeks
- Taiwan grid status — in 1999 the island-wide outage extended fab downtime
Curated by Morrowfly — these are things to check, not monitor conditions.
Make it yours
Your call, in your words — recorded privately on this device, with a check-back in 30, 60, or 90 days.
Tell us
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Read by a human · never auto-published